This invention relates, in general, to semiconductor devices, and more particularly, to an improved method of fabricating a bipolar transistor which is compatible with a method of fabricating CMOS transistors.
When integrating bipolar transistors with MOS transistors, compromises must be made to either the MOS transistors or the bipolar transistors, or both, in order to integrate the transistors on a single chip. Thus, any improvement which simplifies the BiCMOS fabrication process, or improves the electrical characteristics of the transistors is desirable. Some circuits require the bipolar transistors to have improved performance. In order to fabricate a high performance bipolar transistor, it is essential to minimize base resistance and base-collector capacitance. A reduction in these parameters will improve the switching speed of the bipolar transistor. A bipolar process which is very compatible with the MOS process is desirable to reduce the number of processing steps and the number of photolithography steps. This will allow for an improvement in yield and a decrease in cycle time.
By now it should be appreciated that it would be advantageous to provide an improved method of fabricating a high perfomance bipolar transistor that is also compatible with a method of fabricating CMOS transistors.
Accordingly, it is an object of the present invention to provide an improved method of fabricating a bipolar transistor of a BiCMOS integrated circuit.
Another object of the present invention is to provide an improved method of fabricating a bipolar transistor having a reduced base resistance.
A futher object of the present invention is to provide a method of fabricating a bipolar transistor having a self-aligned extrinsic base.
An additional object of the present invention is to provide a method of fabricating a bipolar transistor having a reduced base-collector capacitance.
Yet another object of the present invention is to provide a method of fabricating a bipolar transistor utilizing two polysilicon layers.